(1) Field of the Invention
The present invention relates to a multiplier composed of an integrated semiconductor circuit, and more particularly to a multiplier for multiplying a multiplicand repeatedly by a multiplier.
(2) Description of the Related Art:
FIG. 1 of the accompanying drawings shows in block form a multiplier for multiplying an N-bit multiplicand repeatedly by an M-bit multiplier. As shown in FIG. 1, the multiplier comprises a first register 51 for temporarily storing the M-bit multiplier, a second register 52 for temporarily storing the N-bit multiplicand, an arithmetic unit 60 supplied with output signals from the first and second registers 51, 52 for generating a plurality of partial products and adding the partial products, and a third register 53 for temporarily storing an output signal from the arithmetic unit 60 as a product.
FIG. 2 of the accompanying drawings shows a specific arrangement of the multiplier shown in FIG. 1. Such a multiplier circuit arrangement is disclosed in Japanese Patent Laid-open No. Showa 55-105732. The first and second registers 51, 52 are supplied with an 8-bit multiplier A.sub.1, A.sub.2, .about., A.sub.8 and an 8-bit multiplicand B.sub.1, B.sub.2, .about., B.sub.8. The arithmetic unit 60 comprises a Booth's encoder 54, a rectangular matrix of Booth's selector/adders 55, and a carry select adder 56. The arithmetic unit 60 is supplied with the multiplier A.sub.1, A.sub.2, .about., A.sub.8 and the multiplicand B.sub.1, B.sub.2, .about., B.sub.8, and multiplies the multiplicand by the multiplier according to the Booth's algorithm.
The Booth's encoder 54 is composed of a plurality of encoders 54a for outputting a code corresponding to the multiplier supplied from the first register 51. The Booth's selector/adders 55 select a multiplicand which will become a partial product, based on the code outputted by the Booth's encoder 54, and add a partial product from the Booth's selector/adders 55 in a row positioned thereabove in FIG. 2. The third register 53 receives the result from the arithmetic unit 60, and outputs a product C.sub.1, C.sub.2, .about., C.sub.8. In the multiplier, therefore, the Booth's encoder 54 outputs information (code) for generating partial products based on the Booth's algorithm, the output signal from the Booth's encoder 54 is supplied to the Booth's selectors to generate partial products, and the partial products are added according to the carry/save process at the same time that the partial products are generated.
In FIG. 2, a ground potential GD corresponds to a logic level 0 and a power supply potential VD corresponds to a logic level 1. The multiplier shown in FIG. 2 employs the Booth's algorithm as a multiplication algorithm for generating partial products. The bits of the output signal from the first register 51 are supplied to the corresponding encoders 54a. Output signals from the encoders 54a are supplied as information for generating partial products to the Booth's selector/adders 55 in the respective rows corresponding to the encoders 54a. At this time, the output signals from the encoders 54a are supplied in common to the input terminals of the corresponding Booth's selector/adders 55 for generating partial products corresponding to all the bits of the output signal from the second register 52 and adding the partial products.
FIG. 3 of the accompanying drawings shows a layout and signal wires of the multiplier shown in FIG. 2, the multiplier serving to multiply an N-bit multiplicand by an M-bit multiplier. A first register 71 stores the M-bit multiplier which is given, and a second register 72 stores the N-bit multiplicand which is given. An arithmetic unit 80 comprises a Booth's encoder 74, a rectangular matrix of Booth's selector/adders 75, and a carry select adder 76. The arithmetic unit 80 is supplied with the multiplier and the multiplicand respectively from the first and second registers 71, 72, and multiplies the multiplicand by the multiplier according to the Booth's algorithm. The product produced by the arithmetic unit 80 is stored by a third register 73.
If the product is to be further multiplied by a multiplier, then the contents of the third register 73 are transferred to the second register 72 through output wires L.sub.12 of the third register 73 and input wires L.sub.11 of the second register 72, and a multiplying process similar to the above process is carried out by the arithmetic unit 80. If the contents of the third register 73 are to be passed through another register so as to be transferred to the second register 72, then the contents of the third register 73 are transferred through the output wires L.sub.12, a RAM 77 (see FIG. 4 of the accompanying drawings), and the input wires L.sub.11 to the second register 72.
The multiplier layouts shown in FIGS. 3 and 4 are characterized in that the third register 73 is disposed on a side of the arithmetic unit 80 where a carry select adder 76 is located, and the second register 72 is disposed on a side of the arithmetic unit 80 remote from the carry select adder 76 and extends along an outer edge of the arithmetic unit 80.
With the conventional multiplier layouts, when repeated multiplications are to be carried out, a bus composed of as many wires as the number of bits of data has to be added outside of the multiplier for transferring the data from the third register which temporarily stored the product to the first or second register. Therefore, the multipliers have occupied a large area due to the required bus. For example, the bus can be provided along the sides of the arithmetic unit 80 as shown in FIG. 5.